mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
e7156c644d
genvar declaration cannot take an initial value when declared as a module_or_generate_item_declaration. Correct this test so that it doesn't fail unexpectedly if Yosys aligns with the standard.
27 lines
382 B
Plaintext
27 lines
382 B
Plaintext
read_verilog <<EOT
|
|
module foo;
|
|
|
|
genvar a;
|
|
for (a = 0; a < 10; a++) begin : a
|
|
end : a
|
|
endmodule
|
|
EOT
|
|
read_verilog <<EOT
|
|
module foo2;
|
|
|
|
genvar a;
|
|
for (a = 0; a < 10; a++) begin : a
|
|
end
|
|
endmodule
|
|
EOT
|
|
|
|
logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
|
|
read_verilog <<EOT
|
|
module foo3;
|
|
|
|
genvar a;
|
|
for (a = 0; a < 10; a++) begin : a
|
|
end : b
|
|
endmodule
|
|
EOT
|