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https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
a1a0abf52a
Before this fix, equiv_induct only assumed that one of the following is true: - defined value of A is equal to defined value of B - A is undefined This lets through valuations where A is defined, B is undefined, and the defined (meaningless) value of B happens to match the defined value of A. Instead, tighten this up to OR of the following: - defined value of A is equal to defined value of B, and B is not undefined - A is undefined
36 lines
545 B
Plaintext
36 lines
545 B
Plaintext
read_ilang << EOT
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module \top
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wire $a
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wire $b
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wire input 1 \D
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wire input 2 \EN
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wire output 3 \Q
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cell $mux $x
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parameter \WIDTH 1
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connect \A \Q
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connect \B \D
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connect \S \EN
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connect \Y $a
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end
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cell $ff $y
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parameter \WIDTH 1
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connect \D $a
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connect \Q $b
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end
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cell $and $z
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $b
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connect \B 1'x
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connect \Y \Q
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end
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end
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EOT
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equiv_opt -assert -undef ls
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