yosys/tests/techmap/bug2183.ys at 0c7ac36dcf18ed1afcb2ef5a3011c2a47b8d4118 - mirrors/yosys - Libre-Chip.org

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whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap.

For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.

2020-08-26 16:29:42 +00:00

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 read_verilog <<EOT
 module foo(inout a, b);
   assign a = b;
 endmodule
 module bar(output c);
   foo f(c, 1'b0);
 endmodule
 EOT
 hierarchy -auto-top
 flatten