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26 lines
463 B
Verilog
26 lines
463 B
Verilog
module func_recurse_top(
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input wire [3:0] inp,
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output wire [3:0] out1, out2
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);
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function automatic [3:0] pow_a;
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input [3:0] base, exp;
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begin
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pow_a = 1;
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if (exp > 0)
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pow_a = base * pow_a(base, exp - 1);
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end
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endfunction
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function automatic [3:0] pow_b;
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input [3:0] base, exp;
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begin
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pow_b = 1;
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if (exp > 0)
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pow_b = base * pow_b(base, exp - 1);
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end
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endfunction
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assign out1 = pow_a(inp, 3);
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assign out2 = pow_b(2, 2);
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endmodule
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