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70 lines
654 B
Verilog
Executable file
70 lines
654 B
Verilog
Executable file
`timescale 1ns/1ns
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module tb_dffsr();
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reg clk = 0;
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reg d = 0;
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reg set = 0;
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reg clr = 0;
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wire q;
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dffsr uut(.d(d),.clk(clk),.set(set),.clr(clr),.q(q));
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always
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#(5) clk <= !clk;
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initial
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begin
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$dumpfile("tb_dffsr");
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$dumpvars(0,tb_dffsr);
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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clr = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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clr = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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set = 1;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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set = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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d = 1;
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#10
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d = 0;
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#10
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$finish;
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end
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endmodule
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