mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
9 lines
128 B
Verilog
9 lines
128 B
Verilog
module adlatch( input d, rst, en, output reg q );
|
|
always @* begin
|
|
if (rst)
|
|
q = 0;
|
|
else if (en)
|
|
q = d;
|
|
end
|
|
endmodule
|