3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00
yosys/tests/sat/grom.ys
2022-02-04 10:01:06 +01:00

10 lines
366 B
Plaintext

read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v;
prep -top grom_computer;
sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80
sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp
sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold
sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate