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26 lines
501 B
Verilog
26 lines
501 B
Verilog
module opt_share_test(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input [2:0] sel,
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output reg [31:0] res
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);
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wire [15:0] add0_res = a+d;
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always @* begin
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case(sel)
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0: res = {add0_res, a};
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1: res = {a - b, add0_res[7], 15'b0};
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2: res = {b-a, b};
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3: res = {d, b - c};
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4: res = {d, b - a};
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5: res = {c, d};
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6: res = {a - c, b-d};
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default: res = 32'bx;
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endcase
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end
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endmodule
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