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16 lines
271 B
Verilog
16 lines
271 B
Verilog
module opt_share_test(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [15:0] d,
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input sel,
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output [63:0] res,
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);
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reg [31: 0] cat1 = {a+b, c+d};
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reg [31: 0] cat2 = {a-b, c-d};
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assign res = {b, sel ? cat1 : cat2, a};
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endmodule
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