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15 lines
205 B
Plaintext
15 lines
205 B
Plaintext
read_verilog <<EOT
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module top(input [3:0] A, B, C, input S, output [2:0] O);
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wire [3:0] tb = A + B;
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wire [3:0] tc = A + C;
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assign O = S ? tb[3:1] : tc[3:1];
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endmodule
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EOT
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equiv_opt -assert opt_share
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