mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
11 lines
158 B
Verilog
11 lines
158 B
Verilog
module opt_share_test(
|
|
input [15:0] a,
|
|
input [15:0] b,
|
|
input sel,
|
|
output [15:0] res,
|
|
);
|
|
|
|
assign res = {sel ? a + b : a - b};
|
|
|
|
endmodule
|