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436d42c00c
This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
9 lines
96 B
Verilog
9 lines
96 B
Verilog
module top(...);
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input [7:0] A;
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output [7:0] B;
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wire [7:0] C = 3;
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assign B = A + C;
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endmodule
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