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23 lines
238 B
Plaintext
23 lines
238 B
Plaintext
read_verilog << EOT
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module top(...);
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input [1:0] D;
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input C;
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output O;
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reg [1:0] Q;
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initial Q = 0;
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always @(posedge C)
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Q <= D;
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assign O = Q[1];
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endmodule
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EOT
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synth
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check -assert -initdrv
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select -assert-count 1 a:init=2'b0x
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