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Martin Povišer f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports

If the `$ge` cell we are replacing has wide output port, the upper bits
on the port should be driven to zero. That's not what a `$not` cell with
a single-bit input does. Instead opt for a `$logic_not` cell, which does
zero-pad its output.

Fixes #3867.

2023-08-01 13:50:12 +01:00

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 read_verilog <<EOF
 module test (input signed [4:0] i, output [5:0] o);
 assign o = (i >= 0);
 endmodule
 EOF
 equiv_opt -assert opt_expr -fine