yosys/tests/lut/map_or.v at 0c7ac36dcf18ed1afcb2ef5a3011c2a47b8d4118 - mirrors/yosys - Libre-Chip.org

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whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

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77 B

Verilog

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 module top(...);
     input a, b;
     output y;
     assign y = a|b;
 endmodule