mirror of
https://github.com/YosysHQ/yosys
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4e70c30775
- FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
38 lines
1.3 KiB
Plaintext
38 lines
1.3 KiB
Plaintext
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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design -save orig
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FDRE
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select -assert-count 1 t:LUT4
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select -assert-count 4 t:LUT5
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select -assert-count 1 t:LUT6
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select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D
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design -load orig
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 6 t:FDRE
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select -assert-count 1 t:LUT1
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select -assert-max 1 t:LUT3
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select -assert-max 8 t:LUT4
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select -assert-count 5 t:MUXF5
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select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
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