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9 lines
464 B
Plaintext
9 lines
464 B
Plaintext
read_verilog ../../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 9 t:$lut # OOT flow has 8
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select -assert-count 8 t:adder_carry
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select -assert-none t:$lut t:adder_carry %% t:* %D
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