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27 lines
823 B
Plaintext
27 lines
823 B
Plaintext
read_verilog <<EOT
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// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
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// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
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module top();
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(* keep *) wire [31:0] \a[10] ;
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(* keep *) wire b;
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assign b = \a[10] [31];
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endmodule
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EOT
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synth_intel_alm -family cyclonev -quartus
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select -assert-none w:*[* w:*]*
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design -reset
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read_verilog <<EOT
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// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
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// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
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module top();
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(* keep *) wire [31:0] \a[10] ;
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(* keep *) wire b;
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assign b = \a[10] [31];
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endmodule
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EOT
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synth_intel_alm -family cyclone10gx -quartus -noiopad -noclkbuf
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select -assert-none w:*[* w:*]*
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