3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-05 17:14:08 +00:00
yosys/tests/arch/intel_alm/blockram.ys
KrystalDelusion 8f6a06951c Fix for sync_ram_sdp not being final module
Explicitly declare -top in synth_intel_alm.
2023-02-21 05:23:16 +13:00

8 lines
316 B
Plaintext

read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp
synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf
cd sync_ram_sdp
select -assert-count 1 t:MISTRAL_NOT
select -assert-count 1 t:MISTRAL_M10K
select -assert-none t:MISTRAL_NOT t:MISTRAL_M10K %% t:* %D