mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
81964d6d6f
* remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
25 lines
937 B
Plaintext
25 lines
937 B
Plaintext
read_verilog ../common/mux.v
|
|
design -save read
|
|
|
|
design -load read
|
|
hierarchy -top mux4
|
|
proc
|
|
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux4 # Constrain all select calls below inside the top module
|
|
select -assert-max 1 t:CC_LUT2
|
|
select -assert-max 2 t:CC_LUT4
|
|
select -assert-max 1 t:CC_MX2
|
|
select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
|
|
|
|
design -load read
|
|
hierarchy -top mux8
|
|
proc
|
|
equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd mux8 # Constrain all select calls below inside the top module
|
|
select -assert-max 1 t:CC_LUT3
|
|
select -assert-max 5 t:CC_LUT4
|
|
select -assert-max 1 t:CC_MX2
|
|
select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
|