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24 lines
362 B
Plaintext
24 lines
362 B
Plaintext
read_verilog <<EOT
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module top(
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input clk,
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output reg [15:0] sig1, sig2
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);
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reg [7:0] ptr1, ptr2;
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reg [15:0] mem [0:255];
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initial begin
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$readmemh("bug1836.mem", mem);
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end
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always @(posedge clk) begin
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sig1 <= mem[ptr1];
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ptr1 <= ptr1 + 3;
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sig2 <= mem[ptr2];
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ptr2 <= ptr2 + 7;
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end
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endmodule
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EOT
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synth_ecp5 -top top
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select -assert-count 1 t:DP16KD
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