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acb993b27b
Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
16 lines
285 B
Verilog
16 lines
285 B
Verilog
module dff ( input d, clk, output reg q );
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always @( posedge clk )
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q <= d;
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endmodule
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module dffe( input d, clk, en, output reg q );
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`ifndef NO_INIT
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initial begin
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q = 0;
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end
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`endif
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always @( posedge clk )
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if ( en )
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q <= d;
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endmodule
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