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whitequark 128522f173 verilog_backend: in non-SV mode, add a trigger for always @*. 
This commit only affects translation of RTLIL processes (for which
there is limited support).

Due to the event-driven nature of Verilog, processes like

    reg x;
    always @*
        x <= 1;

may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:

    reg init = 0;
    reg x;
    always @* begin
        if (init) begin end
        x <= 1;
    end

Fixes #2271.
2020-07-16 11:30:14 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc verilog_backend: in non-SV mode, add a trigger for always @*. 2020-07-16 11:30:14 +00:00