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yosys/passes
Natalia 305b6c81d7 Refine width check to allow Y_WIDTH >= natural width
Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).

This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
..
cmds Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
equiv Merge pull request #5357 from rocallahan/builtin-ff 2025-09-17 11:37:16 +02:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
opt Refine width check to allow Y_WIDTH >= natural width 2026-01-14 14:58:53 -08:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat Revert sim's cycle_width default back to 10, but keep -width option 2025-10-20 14:40:05 +02:00
techmap Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00