mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-28 18:29:25 +00:00
217 lines
10 KiB
Text
217 lines
10 KiB
Text
read_rtlil <<EOT
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# Generated by Yosys 0.9+1706 (git sha1 58ab9f60, clang 6.0.0-1ubuntu2 -fPIC -Os)
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autoidx 2815
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:9"
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attribute \cells_not_processed 1
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attribute \dynports 1
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module \ahb_async_sram_halfwidth
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parameter \DEPTH
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parameter \W_ADDR
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parameter \W_BYTEADDR
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parameter \W_DATA
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parameter \W_SRAM_ADDR
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parameter \W_SRAM_DATA
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire $0\addr_lsb[0:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire $0\hready_r[0:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire $0\long_dphase[0:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire width 16 $0\rdata_buf[15:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire $0\read_dph[0:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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wire $0\write_dph[0:0]
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
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wire width 32 $add$../hdl/mem/ahb_async_sram_halfwidth.v:63$2433_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
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wire width 16 $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
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wire $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2450_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2451_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2452_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2453_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2454_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2455_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2456_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2457_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2458_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:112"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:112$2459_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:118$2444_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:133"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:133$2449_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2461_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:140"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:140$2463_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:58$2425_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2426_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2427_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:59$2429_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
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wire $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:104"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:104$2442_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:118$2443_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:125"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:125$2446_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:132$2447_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:59$2428_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:81"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:81$2438_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:83"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:83$2439_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
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wire $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:91$2440_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:118"
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wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:118$2445_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:132"
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wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:132$2448_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:59"
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wire $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
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wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2460_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:139"
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wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:139$2462_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
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wire width 2 $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
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wire width 16 $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
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wire width 8 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2419_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
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wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:54$2420_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
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wire width 2 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
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wire width 32 $shl$../hdl/mem/ahb_async_sram_halfwidth.v:56$2423_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
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wire width 32 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:63$2432_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:65"
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wire width 16 $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:50"
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wire \addr_lsb
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:24"
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wire width 32 \ahbls_haddr
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:28"
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wire width 3 \ahbls_hburst
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:30"
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wire \ahbls_hmastlock
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:29"
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wire width 4 \ahbls_hprot
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:32"
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wire width 32 \ahbls_hrdata
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:22"
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wire \ahbls_hready
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:21"
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wire \ahbls_hready_resp
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:23"
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wire \ahbls_hresp
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:27"
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wire width 3 \ahbls_hsize
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:26"
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wire width 2 \ahbls_htrans
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:31"
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wire width 32 \ahbls_hwdata
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:25"
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wire \ahbls_hwrite
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:56"
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wire \aphase_full_width
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:55"
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wire width 2 \bytemask
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:54"
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wire width 2 \bytemask_noshift
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:17"
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wire \clk
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:46"
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wire \hready_r
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:47"
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wire \long_dphase
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:64"
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wire width 16 \rdata_buf
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:49"
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wire \read_dph
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:18"
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wire \rst_n
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:34"
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wire width 11 \sram_addr
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:39"
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wire width 2 \sram_byte_n
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:36"
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wire \sram_ce_n
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:35"
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wire width 16 \sram_dq
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:38"
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wire \sram_oe_n
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:61"
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wire width 16 \sram_q
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:62"
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wire width 16 \sram_rdata
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:63"
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wire width 16 \sram_wdata
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:37"
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wire \sram_we_n
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:58"
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wire \we_next
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:48"
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wire \write_dph
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:71"
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process $proc$../hdl/mem/ahb_async_sram_halfwidth.v:71$2436
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72"
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switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y
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case 1'1
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case
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78"
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switch \ahbls_hready
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case 1'1
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79"
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switch \ahbls_htrans [1]
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case 1'1
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case
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end
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case
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attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91"
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switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y
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case 1'1
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case
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end
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end
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end
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sync posedge \clk
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sync negedge \rst_n
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end
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connect \ahbls_hresp 1'0
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connect \bytemask_noshift $not$../hdl/mem/ahb_async_sram_halfwidth.v:54$2421_Y
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connect \bytemask $shl$../hdl/mem/ahb_async_sram_halfwidth.v:55$2422_Y
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connect \aphase_full_width $eq$../hdl/mem/ahb_async_sram_halfwidth.v:56$2424_Y
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connect \we_next $logic_or$../hdl/mem/ahb_async_sram_halfwidth.v:59$2430_Y
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connect \sram_rdata $and$../hdl/mem/ahb_async_sram_halfwidth.v:62$2431_Y
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connect \sram_wdata $shiftx$../hdl/mem/ahb_async_sram_halfwidth.v:63$2434_Y
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connect \ahbls_hrdata { \sram_rdata $ternary$../hdl/mem/ahb_async_sram_halfwidth.v:65$2435_Y }
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connect \ahbls_hready_resp \hready_r
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end
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EOT
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synth_ice40 -abc2 -abc9
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