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16 lines
270 B
Text
16 lines
270 B
Text
# Swapping names for two ports
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logger -expect error "not declared in module header" 1
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read_verilog << EOF
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module gate_swap (
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.a(b),
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.b(a),
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c
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);
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input a;
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input b;
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output c;
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assign c = a & !b;
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endmodule
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EOF
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logger -check-expected
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design -reset
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