yosys/tests/verilog/port_rename_error_1.ys

# Multiple names for the same inout port
logger -expect error "Missing details for module port" 1
read_verilog << EOF
module gate_multi_inout (
    .i(a),
    .o(a)
);
    inout a;
endmodule
EOF
logger -check-expected
design -reset