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https://github.com/YosysHQ/yosys
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d41688f7d7
* area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com>
53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
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parameter addr_width = 10;
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parameter data_width = 2;
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input clka,clkb,wea,web;
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input [data_width - 1 : 0] dataina,datainb;
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input [addr_width - 1 : 0] addra,addrb;
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output reg [data_width - 1 : 0] qa,qb;
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reg [addr_width - 1 : 0] addra_reg, addrb_reg;
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reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
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always @ (posedge clka)
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begin
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addra_reg <= addra;
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if(wea) begin
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mem[addra] <= dataina;
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qa <= dataina;
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end else begin
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qa <= mem[addra];
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end
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end
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always @ (posedge clkb)
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begin
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addrb_reg <= addrb;
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if(web) begin
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mem[addrb] <= datainb;
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qb <= datainb;
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end else begin
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qb <= mem[addrb];
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end
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end
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endmodule
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