mirror of
https://github.com/YosysHQ/yosys
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79 lines
1.2 KiB
Text
79 lines
1.2 KiB
Text
ram block $__CC_BRAM_TDP_ {
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option "MODE" "20K" {
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abits 14;
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widths 1 2 5 10 20 per_port;
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cost 129;
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}
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option "MODE" "40K" {
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abits 15;
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widths 1 2 5 10 20 40 per_port;
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cost 257;
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}
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option "MODE" "CASCADE" {
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abits 16;
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# hack to enforce same INIT layout as in the other modes
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widths 1 2 5 per_port;
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cost 513;
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}
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byte 1;
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init no_undef;
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port srsw "A" "B" {
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clock anyedge;
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clken;
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option "MODE" "20K" {
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width mix;
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}
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option "MODE" "40K" {
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width mix;
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}
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option "MODE" "CASCADE" {
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width mix 1;
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}
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portoption "WR_MODE" "NO_CHANGE" {
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rdwr no_change;
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}
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portoption "WR_MODE" "WRITE_THROUGH" {
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rdwr new;
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}
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wrbe_separate;
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optional_rw;
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}
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}
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ram block $__CC_BRAM_SDP_ {
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option "MODE" "20K" {
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abits 14;
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widths 1 2 5 10 20 40 per_port;
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cost 129;
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}
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option "MODE" "40K" {
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abits 15;
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widths 1 2 5 10 20 40 80 per_port;
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cost 257;
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}
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byte 1;
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init no_undef;
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port sr "R" {
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option "MODE" "20K" {
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width 40;
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}
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option "MODE" "40K" {
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width 80;
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}
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clock anyedge;
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clken;
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optional;
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}
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port sw "W" {
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option "MODE" "20K" {
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width 40;
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}
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option "MODE" "40K" {
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width 80;
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}
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clock anyedge;
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clken;
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wrbe_separate;
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optional;
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}
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}
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