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Code Activity
yosys/techlibs/gatemate
History
Patrick Urban 0a72952d5f synth_gatemate: Apply review remarks 
* remove unused techmap models in `map_regs.v`
* replace RAM initilization loops with 320-bit-writes
* add script to test targets in top-level Makefile
* remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v`
* iterate over all modules in `gatemate_bramopt` pass
2021-11-13 21:53:25 +01:00
..
arith_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams.txt synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_20.vh synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_init_40.vh synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
brams_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
cells_bb.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
cells_sim.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
gatemate_bramopt.cc synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
iob_map.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
lut_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
Makefile.inc synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
mul_map.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
mux_map.v synth_gatemate: Initial implementation 2021-11-13 21:53:25 +01:00
reg_map.v synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00
synth_gatemate.cc synth_gatemate: Apply review remarks 2021-11-13 21:53:25 +01:00