mirror of
https://github.com/YosysHQ/yosys
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0a72952d5f
* remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass |
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| .. | ||
| arith_map.v | ||
| brams.txt | ||
| brams_init_20.vh | ||
| brams_init_40.vh | ||
| brams_map.v | ||
| cells_bb.v | ||
| cells_sim.v | ||
| gatemate_bramopt.cc | ||
| iob_map.v | ||
| lut_map.v | ||
| Makefile.inc | ||
| mul_map.v | ||
| mux_map.v | ||
| reg_map.v | ||
| synth_gatemate.cc | ||