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yosys/tests/verilog/bug4785.ys
Krystine Sherwin 0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 12:15:54 +13:00

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logger -expect error "Cell arrays of primitives are currently not supported" 1
read_verilog <<EOT
module test(in1, in2, out1);
input in1, in2;
output out1;
nand #2 t_nand[0:7](out1, in1, in2);
endmodule
EOT