Zachary Snow e833c6a418 verilog: use derived module info to elaborate cell connections ... - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change		2021-10-25 18:25:50 -07:00
..
aiger	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
ast	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
blif	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
json	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
liberty	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	Specify minimum bison version 3.0+	2021-10-01 21:18:33 -06:00
verific	Compile option for enabling async load verific support	2021-10-25 09:04:43 +02:00
verilog	Specify minimum bison version 3.0+	2021-10-01 21:18:33 -06:00