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19 lines
463 B
Text
19 lines
463 B
Text
# https://github.com/YosysHQ/yosys/issues/892
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read_verilog <<EOT
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module top (input clk, sel, di, output do);
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reg [0:1] data [0:0];
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always @(posedge clk)
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data[0] <= {di, data[0][0]};
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assign do = data[0][sel];
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endmodule
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EOT
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proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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design -load postopt
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select -assert-count 1 t:BUFG
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select -assert-count 2 t:FDRE
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select -assert-count 1 t:LUT3
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select -assert-none t:BUFG t:FDRE t:LUT3 %% t:* %D
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