mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
7 lines
151 B
Verilog
7 lines
151 B
Verilog
module string_format_top;
|
|
parameter STR = "something interesting";
|
|
initial begin
|
|
$display("A: %s", STR);
|
|
$display("B: %0s", STR);
|
|
end
|
|
endmodule
|