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With this change, it is easier to see which signals carry state (only wire<>s appear as `reg` in VCD files) and to construct a minimal checkpoint (CXXRTL_WIRE debug items represent the canonical smallest set of state required to fully reconstruct the simulation). |
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.. | ||
cxxrtl.h | ||
cxxrtl_backend.cc | ||
cxxrtl_capi.cc | ||
cxxrtl_capi.h | ||
cxxrtl_vcd.h | ||
cxxrtl_vcd_capi.cc | ||
cxxrtl_vcd_capi.h | ||
Makefile.inc |