Eddie Hung 5562cb08a4 Use single DSP_SIGNEDONLY macro		2019-07-18 13:09:55 -07:00
..
tests
.gitignore
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v	xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)	2019-07-16 16:47:53 +01:00
cells_sim.v	Signedness	2019-07-16 15:54:27 -07:00
cells_xtra.sh
cells_xtra.v	Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim	2019-07-15 11:13:22 -07:00
drams.txt
drams_map.v
dsp_map.v	Make all operands signed	2019-07-17 14:25:40 -07:00
ff_map.v	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
lut_map.v
Makefile.inc	Oops forgot these files	2019-07-15 15:03:15 -07:00
mux_map.v
synth_xilinx.cc	Use single DSP_SIGNEDONLY macro	2019-07-18 13:09:55 -07:00
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc7_brams.txt
xc7_brams_bb.v
xc7_brams_map.v