Xiretza 092e923330 verilog: fix buf/not primitives with multiple outputs ... From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.		2021-03-17 11:44:03 -04:00
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aiger	Provide an integer implementation of decimal_digits().	2021-02-01 11:23:44 -08:00
ast	verilog: fix buf/not primitives with multiple outputs	2021-03-17 11:44:03 -04:00
blif	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
json	json: Add support for memories.	2021-03-15 17:19:19 +01:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	Add support for memory writes in processes.	2021-03-08 20:16:29 +01:00
verific	Update README	2021-03-04 16:43:30 +01:00
verilog	sv: support for parameters without default values	2021-03-02 10:43:53 -05:00