mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
10 lines
329 B
Systemverilog
10 lines
329 B
Systemverilog
module top_properties (input logic clock, read, write, ready);
|
|
a_rw: assert property ( @(posedge clock) !(read && write) );
|
|
`ifdef FAIL
|
|
a_wr: assert property ( @(posedge clock) write |-> ready );
|
|
`else
|
|
a_wr: assert property ( @(posedge clock) write |=> ready );
|
|
`endif
|
|
endmodule
|
|
|
|
bind top top_properties properties_inst (.*);
|