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24 lines
929 B
Plaintext
24 lines
929 B
Plaintext
read_verilog -icells <<EOT
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module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q);
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(* init = 1'b1 *)
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wire unused;
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$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
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$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
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$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
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$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
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$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
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$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
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$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
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$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
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$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8]));
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$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
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endmodule
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EOT
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equiv_opt -map +/simcells.v -multiclock zinit
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design -load postopt
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select -assert-count 1 w:unused a:init %i
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