This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-10-24 08:24:35 +00:00
Code
Activity
08ceb3729e
yosys
/
passes
History
Clifford Wolf
2279b2a196
Added "add" command (only wires for now)
2013-11-20 19:37:40 +01:00
..
abc
Renamed temp module generated by "abc" pass from "logic" to "netlist"
2013-11-19 01:03:57 +01:00
cmds
Added "add" command (only wires for now)
2013-11-20 19:37:40 +01:00
extract
Automatically run "proc" on extract map files
2013-07-24 20:19:08 +02:00
fsm
Added detection for endless recursion in fsm_detect pass
2013-10-30 00:47:58 +01:00
hierarchy
Added resolution of positional arguments to hierarchy pass
2013-11-03 09:42:51 +01:00
memory
Fixed help message typo (memory pass)
2013-10-30 00:47:31 +01:00
opt
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
proc
Added support for complex set-reset flip-flops in proc_dff
2013-10-24 16:54:05 +02:00
sat
Improved user-friendliness of "sat" and "eval" expression parsing
2013-11-09 12:02:27 +01:00
scc
fixed typos
2013-03-18 07:28:31 +01:00
submod
Renamed opt_rmunused to opt_clean
2013-06-05 07:07:31 +02:00
techmap
Call internal checker more often
2013-11-10 23:24:21 +01:00