mirror of
https://github.com/YosysHQ/yosys
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081d9318bc
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
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| .. | ||
| .gitignore | ||
| add_sub.ys | ||
| adffs.ys | ||
| bug1597.ys | ||
| bug1598.ys | ||
| bug1626.ys | ||
| bug1644.il.gz | ||
| bug1644.ys | ||
| counter.ys | ||
| dffs.ys | ||
| dpram.v | ||
| dpram.ys | ||
| fsm.ys | ||
| ice40_dsp.ys | ||
| ice40_opt.ys | ||
| ice40_wrapcarry.ys | ||
| latches.ys | ||
| logic.ys | ||
| macc.v | ||
| macc.ys | ||
| memories.ys | ||
| mul.ys | ||
| mux.ys | ||
| rom.v | ||
| rom.ys | ||
| run-test.sh | ||
| shifter.ys | ||
| tribuf.ys | ||