mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
081d9318bc
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
285 lines
11 KiB
Plaintext
285 lines
11 KiB
Plaintext
# ================================ RAM ================================
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# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
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select -assert-count 180 t:TRELLIS_FF
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# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # too inefficient
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select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
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select -assert-count 90 t:TRELLIS_FF
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# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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# ================================ ROM ================================
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# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
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select -assert-min 18 t:LUT4
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# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # too inefficient
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select -assert-min 9 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 9 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 9 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
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select -assert-min 9 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
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select -assert-min 9 t:LUT4
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