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yosys/techlibs/ice40
History
Eddie Hung cb505c50d3 Remove debug
2019-07-22 16:14:15 -07:00
..
tests ice40: Fix test_dsp_model.sh 2019-07-19 17:33:57 +01:00
.gitignore
abc_hx.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_hx.lut Fix rename 2019-04-18 09:04:34 -07:00
abc_lp.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_lp.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
abc_u.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_u.lut Rename to abc_*.{box,lut} 2019-04-18 09:02:58 -07:00
arith_map.v $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
brams.txt
brams_init.py
brams_map.v ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 2019-02-28 16:23:40 -08:00
cells_map.v $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
cells_sim.v ice40/cells_sim.v: Fix sign of J and K partial products 2019-07-19 17:33:41 +01:00
ice40_braminit.cc Fix typo in ice40_braminit help msg 2019-03-09 13:24:55 -08:00
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
ice40_unlut.cc ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 2019-07-16 23:57:15 +02:00
latches_map.v
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
synth_ice40.cc Remove debug 2019-07-22 16:14:15 -07:00