This website requires JavaScript.
Explore
Help
Register
Sign in
mirrors
/
yosys
Watch
3
Star
0
Fork
You've already forked yosys
0
mirror of
https://github.com/YosysHQ/yosys
synced
2025-12-04 11:06:46 +00:00
Code
Activity
0795b3ec07
yosys
/
techlibs
/
sf2
History
Stefan Riesenberger
a58571d0fe
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
..
arith_map.v
cells_map.v
cells_sim.v
sf2: fix name of AND modules
2021-04-09 16:46:05 +02:00
Makefile.inc
synth_sf2.cc