Zachary Snow 0795b3ec07 verilog: fix case expression sign and width handling ... - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements		2021-05-25 16:16:46 -04:00
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aiger	Provide an integer implementation of decimal_digits().	2021-02-01 11:23:44 -08:00
ast	verilog: fix case expression sign and width handling	2021-05-25 16:16:46 -04:00
blif	blif: Use library cells' start_offset and upto for wideports.	2021-05-08 15:50:03 +02:00
json	Remove duplicates from conns array in JSON front-end, fixes #2736	2021-04-26 16:32:12 +02:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	Add support for memory writes in processes.	2021-03-08 20:16:29 +01:00
verific	Update README	2021-03-04 16:43:30 +01:00
verilog	sv: support remaining assignment operators	2021-05-25 16:15:57 -04:00