Eddie Hung 42f8e68e76 OUT port to Y in generic DSP		2019-07-15 14:45:47 -07:00
..
.gitignore	ecp5: First BRAM type maps successfully	2018-10-10 16:35:19 +01:00
abc_5g.box	Fix DO4 typo	2019-06-28 09:45:40 -07:00
abc_5g.lut	ecp5: Add abc9 option	2019-06-14 17:15:02 +01:00
abc_5g_nowide.lut	Add _nowide variants of LUT libraries in -nowidelut flows	2019-06-26 10:23:29 -07:00
arith_map.v	ecp5: Improve mapping of $alu when BI is used	2019-06-21 09:45:11 +01:00
bram.txt	ecp5: First BRAM type maps successfully	2018-10-10 16:35:19 +01:00
brams_connect.py	ecp5: Script for BRAM IO connections	2018-10-10 16:11:00 +01:00
brams_init.py	ecp5: First BRAM type maps successfully	2018-10-10 16:35:19 +01:00
brams_map.v	ecp5: Disable LSR inversion	2018-10-16 12:48:39 +01:00
cells_bb.v	ecp5: Add DDRDLLA	2019-02-19 19:34:37 +00:00
cells_map.v	Merge origin/master	2019-06-27 11:20:15 -07:00
cells_sim.v	Disable boxing of ECP5 dist RAM due to regression	2019-06-28 09:46:36 -07:00
dram.txt	ecp5: Don't map ROMs to DRAM	2018-10-01 18:34:41 +01:00
drams_map.v	ecp5: Adding DRAM map	2018-07-13 14:08:42 +02:00
dsp_map.v	OUT port to Y in generic DSP	2019-07-15 14:45:47 -07:00
ecp5_ffinit.cc	ecp5: Demote conflicting FF init values to a warning	2019-03-04 11:26:20 +00:00
latches_map.v	ecp5: Add latch inference	2018-10-19 15:16:40 +01:00
Makefile.inc	Add mul2dsp multiplier splitting rule and ECP5 mapping	2019-07-08 18:42:09 +01:00
synth_ecp5.cc	Merge remote-tracking branch 'origin/master' into xc7dsp	2019-07-10 15:58:01 -07:00