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yosys/techlibs/ecp5
2020-08-07 13:21:03 +02:00
..
tests
.gitignore
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt
brams_connect.py
brams_init.py
brams_map.v
cells_bb.v ecp5: Add missing SERDES parameters 2020-05-12 21:12:26 +01:00
cells_ff.vh
cells_io.vh
cells_map.v ecp5: Use dfflegalize. 2020-07-05 18:49:41 +02:00
cells_sim.v ecp5: TRELLIS_FF bypass path only in async mode 2020-05-14 10:33:56 -07:00
dsp_map.v ecp5: Force SIGNED ports to be 1 bit 2020-04-16 16:38:19 +01:00
ecp5_gsr.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
latches_map.v
lutrams.txt
lutrams_map.v
Makefile.inc ecp5: Use dfflegalize. 2020-07-05 18:49:41 +02:00
synth_ecp5.cc Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00