mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-27 02:58:48 +00:00
5 lines
64 B
Verilog
5 lines
64 B
Verilog
module a;
|
|
wire [5:0]x;
|
|
wire [3:0]y;
|
|
assign y = (4)55;
|
|
endmodule
|