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61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Cyclone IV devices Input Buffer Primitive */
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module cycloneiv_io_ibuf
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(output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // cycloneiv_io_ibuf
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/* Altera Cyclone IV devices Output Buffer Primitive */
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module cycloneiv_io_obuf
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(output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // cycloneiv_io_obuf
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/* Altera Cyclone IV LUT Primitive */
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module cycloneiv_lcell_comb
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(output combout, cout,
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input dataa, datab, datac, datad, cin);
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parameter lut_mask = 16'hFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "cycloneiv_lcell_comb";
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parameter sum_lutc_input = "datac";
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endmodule // cycloneiv_lcell_comb
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/* Altera D Flip-Flop Primitive */
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module dffeas
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(output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload);
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// Timing simulation is not covered
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q_tmp;
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wire reset;
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reg [7:0] debug_net;
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assign reset = (prn && sclr && ~clrn && ena);
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assign q = q_tmp & 1'b1;
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always @(posedge clk, posedge aload) begin
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if(reset) q_tmp <= 0;
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else q_tmp <= d;
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end
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assign q = q_tmp;
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endmodule // dffeas
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