Eddie Hung 9fa0e03cc9 Merge pull request #1632 from YosysHQ/eddie/fix1630 ... read_aiger: uniquify wires with $aiger<autoidx> prefix		2020-01-14 11:40:40 -08:00
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anlogic	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
common	Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram	2019-12-16 21:48:21 -08:00
ecp5	Add #1630 testcase	2020-01-13 21:27:53 -08:00
efinix	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
gowin	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
ice40	Add #1626 testcase	2020-01-12 15:21:26 -08:00
xilinx	this one is fine	2020-01-10 15:20:50 +01:00
run-test.sh	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00